// Copyright (C) 1953-2023 NUDT
// Verilog module name - frame_submission_control   
// Version: V4.3.0.20230309
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         Descriptor Send
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps
 
module frame_submission_control 
(
        i_clk,
        i_rst_n,
        
        iv_desp          ,     
        i_desp_wr        ,
        
        o_desp_wr_hcp    ,
        ov_desp_hcp      ,
        
        o_desp_wr_host   ,
        ov_desp_host
    );

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;
//input
input       [35:0]      iv_desp;
input                   i_desp_wr;

output  reg             o_desp_wr_hcp;
output  reg [11:0]      ov_desp_hcp;

output  reg             o_desp_wr_host;
output  reg [11:0]      ov_desp_host;
//temp ov_descriptor and ov_pkt for discarding pkt while the fifo_used_findows is over the threshold 
//internal wire&reg
        
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        o_desp_wr_hcp          <= 1'b0;
        ov_desp_hcp            <= 12'b0;
        
        o_desp_wr_host        <= 1'b0;
        ov_desp_host          <= 12'b0;	
    end
    else begin
        if(i_desp_wr)begin
            if(iv_desp[35:20] == 16'hff01)begin
                if(iv_desp[19:12] == 8'h5)begin//时间通告
                    o_desp_wr_hcp          <= 1'b0;
                    ov_desp_hcp            <= 12'b0;	
                    
                    o_desp_wr_host        <= i_desp_wr;
                    ov_desp_host          <= iv_desp;
                end
                else begin
                    o_desp_wr_hcp          <= i_desp_wr;
                    ov_desp_hcp            <= iv_desp;
                    
                    o_desp_wr_host        <= 1'b0;
                    ov_desp_host          <= 12'b0;	
                end                                      
            end
            else begin
                o_desp_wr_hcp          <= 1'b0;
                ov_desp_hcp            <= 12'b0;	
                
                o_desp_wr_host        <= i_desp_wr;
                ov_desp_host          <= iv_desp;            
            end
        end
        else begin
            o_desp_wr_hcp          <= 1'b0;
            ov_desp_hcp            <= 12'b0;
            
            o_desp_wr_host        <= 1'b0;
            ov_desp_host          <= 12'b0;	        
        end                  												                     
    end
end
endmodule